1. Field of the Invention
The present invention relates to a semiconductor device. More specifically the present invention relates to a semiconductor device having two or more laminated semiconductor chips.
2. Background Art
FIG. 5 is a schematic sectional view for illustrating a conventional semiconductor device. FIG. 6 is a partially perspective schematic top view for illustrating a conventional semiconductor device. FIG. 7 is a schematic diagram for illustrating a constitution of a DRAM, which is a typical conventional memory.
As shown in FIG. 5, in a semiconductor device 300, a lower semiconductor chip 44 is mounted on the substrate 42, and an upper semiconductor chip 46 is mounted on the center portion of the lower semiconductor chip 44.
Solder balls 50 are formed on a back of the substrate 42. On the other hand, as shown in FIG. 6, bonding pads 52 and 54 are squarely arranged along circumferences of the semiconductor chips 44 and 46. Also as shown in FIGS. 5 and 6, an end of each of wires 56 and 58 is connected to each of the bonding pads 52 and 54, respectively, and the other end of each of wires 56 and 58 is connected to each of solder balls 50.
As described above, in each of the semiconductor chips 44 and 46, the bonding pads 52 and 54 are squarely arranged along the circumferences thereof, respectively. When such semiconductor chips 44 and 46 are stacked in two levels and packaged as in the semiconductor device 300, wires 56 must be connected to the bonding pads 52 of the lower semiconductor chip 44, which is disposed in the lower level, therefore, it is necessary that the upper semiconductor chip 46 does not overlap the bonding pads 52. Consequently, the upper semiconductor chip 46 must be smaller than the lower semiconductor chip 44 by the space for arranging the bonding pads 52.
Therefore, in the case of the constitution like the semiconductor device 300, the lower semiconductor chip cannot be the same as, or of the same size as the upper semiconductor chip. That is, this means that since two or more memory ICs of the same size cannot be stacked in the semiconductor device, and a size of the upper semiconductor chip is limited, increase in a capacity of the memory ICs is also limited.
As shown in FIG. 7, in a semiconductor chip 60 packaged in a DRAM, which is a typical conventional memory, bonding pads 62 are often arranged in line on a center portion thereof. In such a case, if the same semiconductor chip is to be further stacked on the semiconductor chip 60, the upper semiconductor chip overlaps the bonding pads 62. Therefore, a plurality of semiconductor chips cannot be stacked when such semiconductor chips are packaged.